Novel symmetrical buffer design for VLSI applications

Hwang Cherng Chow; Wu Shiung Feng

Novel symmetrical buffer design for VLSI applications

Hwang Cherng Chow^*, Wu Shiung Feng

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Contribution to conference › Conference Paper › peer-review

Abstract

Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

Original language	English
Pages	176-179
Number of pages	4
State	Published - 2000
Event	43rd Midwest Circuits and Systems Conference (MWSCAS-2000) - Lansing, MI, United States Duration: 08 08 2000 → 11 08 2000

Conference

Conference	43rd Midwest Circuits and Systems Conference (MWSCAS-2000)
Country/Territory	United States
City	Lansing, MI
Period	08/08/00 → 11/08/00

Cite this

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title = "Novel symmetrical buffer design for VLSI applications",

abstract = "Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.",

author = "Chow, {Hwang Cherng} and Feng, {Wu Shiung}",

year = "2000",

language = "英语",

pages = "176--179",

note = "43rd Midwest Circuits and Systems Conference (MWSCAS-2000) ; Conference date: 08-08-2000 Through 11-08-2000",

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AU - Chow, Hwang Cherng

AU - Feng, Wu Shiung

PY - 2000

Y1 - 2000

N2 - Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

AB - Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts [9], [1], the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays.

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M3 - 论文

AN - SCOPUS:0034465267

SP - 176

EP - 179

T2 - 43rd Midwest Circuits and Systems Conference (MWSCAS-2000)

Y2 - 8 August 2000 through 11 August 2000

ER -

Novel symmetrical buffer design for VLSI applications

Abstract

Conference

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