Novel VLSI architecture for Lempel-Ziv based data compression

Yeong Kang Lai*, Kuo Chen Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.

Original languageEnglish
Pages (from-to)V-617-V-620
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 2000
Externally publishedYes
EventProceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland
Duration: 28 05 200031 05 2000

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