Novel VLSI architecture for Lempel-Ziv based data compression

Yeong Kang Lai; Kuo Chen Chen

doi:10.1109/ISCAS.2000.857523

Novel VLSI architecture for Lempel-Ziv based data compression

Yeong Kang Lai^*, Kuo Chen Chen

^*Corresponding author for this work

National Dong Hwa University

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.

Original language	English
Pages (from-to)	V-617-V-620
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2000.857523
State	Published - 2000
Externally published	Yes
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 05 2000 → 31 05 2000

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10.1109/ISCAS.2000.857523

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AB - In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, Parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application.

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Novel VLSI architecture for Lempel-Ziv based data compression

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