On Harmonizing Data Lifetime and Block Retention Time for Flash Devices

As the high-density flash memory, such as triple-level-cell (TLC) and 3D flash memory, has gradually dominated the market share, flash-memory-based storage devices also have suffered from the exacerbated performance and endurance problems. In order to improve the endurance of flash devices, wear-leveling and refreshing designs were proposed to evenly distribute erase operations among all flash blocks and to timely correct and re-write data of flash blocks, respectively. However, as these designs mainly aim at enhancing the endurance for flash devices, the performance issue is getting aggravated instead. Such contradiction between performance and endurance improvements drives this research to propose a time harmonization strategy, which harmonizes the block retention time with the data lifetime to enhance performance of flash devices with limited sacrifice to endurance. The experiments were conducted on trace-driven simulation with intensive and realistic workloads. Compared with the existing designs, the proposed design can effectively reduce the redundant writes by 26.8% with merely degrading the overall endurance by 0.4% on average.