Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Minchen Chang*, Jengping Lin, Ruey Dar Chang, Steven N. Shih, Chao Sung Lai, Pei Ing Lee

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

Abstract

The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

Original languageEnglish
Pages307-310
Number of pages4
StatePublished - 2004
EventProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan
Duration: 05 07 200408 07 2004

Conference

ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country/TerritoryTaiwan
Period05/07/0408/07/04

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