Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Minchen Chang; Jengping Lin; Ruey Dar Chang; Steven N. Shih; Chao Sung Lai; Pei Ing Lee

Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Minchen Chang^*
, Jengping Lin
, Ruey Dar Chang
, Steven N. Shih
, Chao Sung Lai
, Pei Ing Lee

^*Corresponding author for this work

Department of Electronic Engineering

Research output: Contribution to conference › Conference Paper › peer-review

1 Scopus citations

Abstract

The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

Original language	English
Pages	307-310
Number of pages	4
State	Published - 2004
Event	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan Duration: 05 07 2004 → 08 07 2004

Conference

Conference	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country/Territory	Taiwan
Period	05/07/04 → 08/07/04

Cite this

@conference{c78aee3fe2774fe2ba713099447cc03e,

title = "Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias",

abstract = "The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.",

author = "Minchen Chang and Jengping Lin and Chang, \{Ruey Dar\} and Shih, \{Steven N.\} and Lai, \{Chao Sung\} and Lee, \{Pei Ing\}",

year = "2004",

language = "英语",

pages = "307--310",

note = "Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 ; Conference date: 05-07-2004 Through 08-07-2004",

}

Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias. / Chang, Minchen; Lin, Jengping; Chang, Ruey Dar et al.
2004. 307-310 Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.

Research output: Contribution to conference › Conference Paper › peer-review

TY - CONF

T1 - Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

AU - Chang, Minchen

AU - Lin, Jengping

AU - Chang, Ruey Dar

AU - Shih, Steven N.

AU - Lai, Chao Sung

AU - Lee, Pei Ing

PY - 2004

Y1 - 2004

N2 - The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

AB - The data retention time performance of 256Mbit DRAM is degraded even in 250°C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of a array transistor is the root cause of retention degradation.

UR - https://www.scopus.com/pages/publications/14844288338

M3 - 论文

AN - SCOPUS:14844288338

SP - 307

EP - 310

T2 - Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004

Y2 - 5 July 2004 through 8 July 2004

ER -

Packaging process induced retention degradation of 256Mbit DRAM with negative wordline bias

Abstract

Conference

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