Paralleled Hardware Annealing for Optimal Solutions on Electronic Neural Networks

Bang W. Lee, Bing J. Sheu

Research output: Contribution to journalJournal Article peer-review

20 Scopus citations

Abstract

Artificial neural networks are very powerful in scientific and engineering applications due to the inherent data classification capabilities and massively parallel processing power. Three basic network schemes have been extensively studied by researchers: the iterative networks, the back propagation networks, and the self-organizing networks. Simulated annealing is a probabilistic hill-climbing technique which accepts, with a nonzero but gradually decreasing probability, deterioration in the cost function of the optimization problems. Hardware annealing combines the simulated annealing technique with continuous-time electronic neural networks by changing the voltage gain of neurons. A Hopfield network is an iterative network which is composed of one-layered neurons with fully connected synapses and can be used to realize associative memories, pattern classifiers, and optimization circuits. Due to the feedback characteristics of the Hopfield networks, the solutions often get stuck at local minima where the cost functions have surrounding barriers. The initial and final voltage gains for applying hardware annealing to Hopfield data-conversion networks are presented. In hardware annealing, the voltage gain of output neurons is increased from an initial low value to a final high value in a continuous fashion which helps to achieve the optimal solution for an optimization problem in one annealing cycle. Experimental results on the transfer function and transient response of electronic neural networks achieving the global minimum are presented.

Original languageEnglish
Pages (from-to)588-599
Number of pages12
JournalIEEE Transactions on Neural Networks
Volume4
Issue number4
DOIs
StatePublished - 07 1993
Externally publishedYes

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