Paralleled Hardware Annealing in Multilevel Hopfield Neural Networks for Optimal Solutions

Sa Hyun Bang; Oscal T.C. Chen; Josephine C.F. Chang; Bing J. Sheu

doi:10.1109/82.363542

Paralleled Hardware Annealing in Multilevel Hopfield Neural Networks for Optimal Solutions

Sa Hyun Bang, Oscal T.C. Chen, Josephine C.F. Chang, Bing J. Sheu

University of Southern California

Research output: Contribution to journal › Journal Article › peer-review

4 Scopus citations

Abstract

In a multilevel neural network, the output of each neuron is to produce a multi-bit representation. Therefore, the total network size can be significantly smaller than a conventional network. The reduction in network size is a highly desirable feature in large-scale applications. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The hardware annealing technique can be applied to the neurons in a parallel format, and is much faster than the simulated annealing method on digital computers.

Original language	English
Pages (from-to)	46-49
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	42
Issue number	1
DOIs	https://doi.org/10.1109/82.363542
State	Published - 01 1995
Externally published	Yes

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abstract = "In a multilevel neural network, the output of each neuron is to produce a multi-bit representation. Therefore, the total network size can be significantly smaller than a conventional network. The reduction in network size is a highly desirable feature in large-scale applications. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The hardware annealing technique can be applied to the neurons in a parallel format, and is much faster than the simulated annealing method on digital computers.",

author = "Bang, {Sa Hyun} and Chen, {Oscal T.C.} and Chang, {Josephine C.F.} and Sheu, {Bing J.}",

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Paralleled Hardware Annealing in Multilevel Hopfield Neural Networks for Optimal Solutions

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