Parallelism tuning according to the deadline for power-gated ILP processors

Yufeng Tong; Yu Liang; Yung Cheng Ma; Wei Zhang

doi:10.1109/ICCPS.2016.7751101

Parallelism tuning according to the deadline for power-gated ILP processors

Yufeng Tong^*, Yu Liang, Yung Cheng Ma, Wei Zhang

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Tianjin University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Digital signal processors (DSP) with very-longinstruction-word (VLIW)processors have been widely used incommunication systems in recent years. It is obvious that parallelism requirement are different between applications, even within an application. As a result, the scheme, which is to partition the application into several regions and assign each region with adapted parallelism, has been proposed. In this paper, we enhance the parallelism assignment stage. The aim is to tune parallelism according to the deadline (the special execution time of users). The proposed algorithm could save more energy with meeting the requirement of users. The experimental results of evaluation with CoreMarkPro benchmark suits show the expected savings of leakage energy. Compared with maximum energy mode, the execution energy could be reduced more than 40% and the execution time just increase less than 10%.

Original language	English
Title of host publication	2016 International Conference on Communication Problem-Solving, ICCP 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509013838
DOIs	https://doi.org/10.1109/ICCPS.2016.7751101
State	Published - 21 11 2016
Event	2016 International Conference on Communication Problem-Solving, ICCP 2016 - Taipei, Taiwan Duration: 07 09 2016 → 09 09 2016

Publication series

Name	2016 International Conference on Communication Problem-Solving, ICCP 2016

Conference

Conference	2016 International Conference on Communication Problem-Solving, ICCP 2016
Country/Territory	Taiwan
City	Taipei
Period	07/09/16 → 09/09/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

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10.1109/ICCPS.2016.7751101

Cite this

Tong, Y., Liang, Y., Ma, Y. C., & Zhang, W. (2016). Parallelism tuning according to the deadline for power-gated ILP processors. In 2016 International Conference on Communication Problem-Solving, ICCP 2016 Article 7751101 (2016 International Conference on Communication Problem-Solving, ICCP 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCPS.2016.7751101

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title = "Parallelism tuning according to the deadline for power-gated ILP processors",

abstract = "Digital signal processors (DSP) with very-longinstruction-word (VLIW)processors have been widely used incommunication systems in recent years. It is obvious that parallelism requirement are different between applications, even within an application. As a result, the scheme, which is to partition the application into several regions and assign each region with adapted parallelism, has been proposed. In this paper, we enhance the parallelism assignment stage. The aim is to tune parallelism according to the deadline (the special execution time of users). The proposed algorithm could save more energy with meeting the requirement of users. The experimental results of evaluation with CoreMarkPro benchmark suits show the expected savings of leakage energy. Compared with maximum energy mode, the execution energy could be reduced more than 40% and the execution time just increase less than 10%.",

author = "Yufeng Tong and Yu Liang and Ma, {Yung Cheng} and Wei Zhang",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Conference on Communication Problem-Solving, ICCP 2016 ; Conference date: 07-09-2016 Through 09-09-2016",

year = "2016",

month = nov,

day = "21",

doi = "10.1109/ICCPS.2016.7751101",

language = "英语",

series = "2016 International Conference on Communication Problem-Solving, ICCP 2016",

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Tong, Y, Liang, Y, Ma, YC & Zhang, W 2016, Parallelism tuning according to the deadline for power-gated ILP processors. in 2016 International Conference on Communication Problem-Solving, ICCP 2016., 7751101, 2016 International Conference on Communication Problem-Solving, ICCP 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Conference on Communication Problem-Solving, ICCP 2016, Taipei, Taiwan, 07/09/16. https://doi.org/10.1109/ICCPS.2016.7751101

Parallelism tuning according to the deadline for power-gated ILP processors. / Tong, Yufeng; Liang, Yu; Ma, Yung Cheng et al.
2016 International Conference on Communication Problem-Solving, ICCP 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7751101 (2016 International Conference on Communication Problem-Solving, ICCP 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Parallelism tuning according to the deadline for power-gated ILP processors

AU - Tong, Yufeng

AU - Liang, Yu

AU - Ma, Yung Cheng

AU - Zhang, Wei

PY - 2016/11/21

Y1 - 2016/11/21

N2 - Digital signal processors (DSP) with very-longinstruction-word (VLIW)processors have been widely used incommunication systems in recent years. It is obvious that parallelism requirement are different between applications, even within an application. As a result, the scheme, which is to partition the application into several regions and assign each region with adapted parallelism, has been proposed. In this paper, we enhance the parallelism assignment stage. The aim is to tune parallelism according to the deadline (the special execution time of users). The proposed algorithm could save more energy with meeting the requirement of users. The experimental results of evaluation with CoreMarkPro benchmark suits show the expected savings of leakage energy. Compared with maximum energy mode, the execution energy could be reduced more than 40% and the execution time just increase less than 10%.

AB - Digital signal processors (DSP) with very-longinstruction-word (VLIW)processors have been widely used incommunication systems in recent years. It is obvious that parallelism requirement are different between applications, even within an application. As a result, the scheme, which is to partition the application into several regions and assign each region with adapted parallelism, has been proposed. In this paper, we enhance the parallelism assignment stage. The aim is to tune parallelism according to the deadline (the special execution time of users). The proposed algorithm could save more energy with meeting the requirement of users. The experimental results of evaluation with CoreMarkPro benchmark suits show the expected savings of leakage energy. Compared with maximum energy mode, the execution energy could be reduced more than 40% and the execution time just increase less than 10%.

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M3 - 会议稿件

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T3 - 2016 International Conference on Communication Problem-Solving, ICCP 2016

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PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 7 September 2016 through 9 September 2016

ER -

Parallelism tuning according to the deadline for power-gated ILP processors

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