Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL

Srinivas Gude; Chia Chi Chu

doi:10.1109/PESGM.2017.8274027

Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL

Srinivas Gude, Chia Chi Chu

National Tsing Hua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

This paper presents a novel technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). This technique can be used as a pre-filter of conventional phase-locked loop (PLL) for grid synchronization. With this the dynamic performance of the PLL is enhanced even under disturbed grid voltage conditions. In comparison with classical generalized delayed signal cancellation (GDSC) and cascaded delayed signal cancellation (CDSC) techniques, the new MDSC technique provides more flexibility to configure the undesired order of harmonics, improved response time and requires less memory for delay blocks. To further improve the response time of the method, variable time-period MDSC (VT-MDSC) is also proposed. Both qualitative analysis and numerical experiments have been performed to demonstrate advantages of the proposed techniques.

Original language	English
Title of host publication	2017 IEEE Power and Energy Society General Meeting, PESGM 2017
Publisher	IEEE Computer Society
Pages	1-5
Number of pages	5
ISBN (Electronic)	9781538622124
DOIs	https://doi.org/10.1109/PESGM.2017.8274027
State	Published - 29 01 2018
Externally published	Yes
Event	2017 IEEE Power and Energy Society General Meeting, PESGM 2017 - Chicago, United States Duration: 16 07 2017 → 20 07 2017

Publication series

Name	IEEE Power and Energy Society General Meeting
Volume	2018-January
ISSN (Print)	1944-9925
ISSN (Electronic)	1944-9933

Conference

Conference	2017 IEEE Power and Energy Society General Meeting, PESGM 2017
Country/Territory	United States
City	Chicago
Period	16/07/17 → 20/07/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

Delayed Signal Cancellation (DSC)
Grid Synchronization
Phase-Locked loops (PLLs)

Access to Document

10.1109/PESGM.2017.8274027

Cite this

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title = "Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL",

abstract = "This paper presents a novel technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). This technique can be used as a pre-filter of conventional phase-locked loop (PLL) for grid synchronization. With this the dynamic performance of the PLL is enhanced even under disturbed grid voltage conditions. In comparison with classical generalized delayed signal cancellation (GDSC) and cascaded delayed signal cancellation (CDSC) techniques, the new MDSC technique provides more flexibility to configure the undesired order of harmonics, improved response time and requires less memory for delay blocks. To further improve the response time of the method, variable time-period MDSC (VT-MDSC) is also proposed. Both qualitative analysis and numerical experiments have been performed to demonstrate advantages of the proposed techniques.",

keywords = "Delayed Signal Cancellation (DSC), Grid Synchronization, Phase-Locked loops (PLLs)",

author = "Srinivas Gude and Chu, \{Chia Chi\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Power and Energy Society General Meeting, PESGM 2017 ; Conference date: 16-07-2017 Through 20-07-2017",

year = "2018",

month = jan,

day = "29",

doi = "10.1109/PESGM.2017.8274027",

language = "英语",

series = "IEEE Power and Energy Society General Meeting",

publisher = "IEEE Computer Society",

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Gude, S & Chu, CC 2018, Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL. in 2017 IEEE Power and Energy Society General Meeting, PESGM 2017. IEEE Power and Energy Society General Meeting, vol. 2018-January, IEEE Computer Society, pp. 1-5, 2017 IEEE Power and Energy Society General Meeting, PESGM 2017, Chicago, United States, 16/07/17. https://doi.org/10.1109/PESGM.2017.8274027

Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL. / Gude, Srinivas; Chu, Chia Chi.
2017 IEEE Power and Energy Society General Meeting, PESGM 2017. IEEE Computer Society, 2018. p. 1-5 (IEEE Power and Energy Society General Meeting; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL

AU - Gude, Srinivas

AU - Chu, Chia Chi

PY - 2018/1/29

Y1 - 2018/1/29

N2 - This paper presents a novel technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). This technique can be used as a pre-filter of conventional phase-locked loop (PLL) for grid synchronization. With this the dynamic performance of the PLL is enhanced even under disturbed grid voltage conditions. In comparison with classical generalized delayed signal cancellation (GDSC) and cascaded delayed signal cancellation (CDSC) techniques, the new MDSC technique provides more flexibility to configure the undesired order of harmonics, improved response time and requires less memory for delay blocks. To further improve the response time of the method, variable time-period MDSC (VT-MDSC) is also proposed. Both qualitative analysis and numerical experiments have been performed to demonstrate advantages of the proposed techniques.

AB - This paper presents a novel technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). This technique can be used as a pre-filter of conventional phase-locked loop (PLL) for grid synchronization. With this the dynamic performance of the PLL is enhanced even under disturbed grid voltage conditions. In comparison with classical generalized delayed signal cancellation (GDSC) and cascaded delayed signal cancellation (CDSC) techniques, the new MDSC technique provides more flexibility to configure the undesired order of harmonics, improved response time and requires less memory for delay blocks. To further improve the response time of the method, variable time-period MDSC (VT-MDSC) is also proposed. Both qualitative analysis and numerical experiments have been performed to demonstrate advantages of the proposed techniques.

KW - Delayed Signal Cancellation (DSC)

KW - Grid Synchronization

KW - Phase-Locked loops (PLLs)

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T3 - IEEE Power and Energy Society General Meeting

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BT - 2017 IEEE Power and Energy Society General Meeting, PESGM 2017

PB - IEEE Computer Society

T2 - 2017 IEEE Power and Energy Society General Meeting, PESGM 2017

Y2 - 16 July 2017 through 20 July 2017

ER -

Performance enhancement of pre-filtered multiple delayed signal cancellation based PLL

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Keywords

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