Petri nets based FPGA controller of PDP sustainer with half-voltage energy recovery circuit

Jian Long Kuo*, Kai Lun Chao, Li Shiang Lee

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

1 Scopus citations

Abstract

This paper proposes a FPGA controller design of a driver circuit based Petri nets for the Plasma Display Panel (PDP). In such a driver circuit, complicated control logic is required in the PDP sustainer circuit to implement the sustaining voltage waveform. The control logic has the zero-switching behaviour for the driver circuit to provide better efficiency for the driving circuit. Conventionally, the VHDL programmer does not have a systematic way to program the control logic. Time delay problem of logic components in logic controller may occur under high frequency operation. With the help of the proposed Petri nets approach, the VHDL programming for the PDP driver circuit can be easier in a systematic way. Also, this paper illustrates three types of sustainers with Petri nets based FPGA controller. The basic full-bridge and full-voltage sustainers are used to compare the performance with the proposed half-voltage sustainer. Details of the circuit operation are described. From the experimental results, the performance such as efficiency, luminance, and gamma curve are assessed to show the effectiveness of the proposed half-voltage sustainer. It is believed that the proposed Petri nets based control circuit is very powerful for the practical application of the PDP sustainer circuit.

Original languageEnglish
Pages (from-to)292-308
Number of pages17
JournalAsian Journal of Control
Volume12
Issue number3
DOIs
StatePublished - 05 2010
Externally publishedYes

Keywords

  • Electronic design automation (EDA)
  • FPGA controller
  • Half-voltage energy recovery circuit (HVERC)
  • Petri nets
  • Plasma display panel (PDP)
  • Sustainer

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