PHEMT switch yield improvement through feedback from 100% die test

M. C. Tu, Paul Yeh, S. M. Liu, H. Y. Ueng, W. D. Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Yield improvement is an ongoing process in the MMIC production line. The gate lithography process will determine the major part of pHEMT wafer yield. This paper investigates yield improvement through feedback from automatic 100% DC and switching time on wafer testing. The breakdown and time domain test provides a reticle-dependent distribution pattern. This is photolithography process dependent and has been attributed to defocus during stepper exposure at gate level. Feeding this information back to the process engineers enables them to pinpoint the specific process step and improve the process yield.

Original languageEnglish
Title of host publication2009 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2009
StatePublished - 2009
Externally publishedYes
Event2009 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2009 - Tampa, FL, United States
Duration: 18 05 200921 05 2009

Publication series

Name2009 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2009

Conference

Conference2009 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2009
Country/TerritoryUnited States
CityTampa, FL
Period18/05/0921/05/09

Keywords

  • Gate lag
  • Lithography
  • Transient time

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