Physical and reliability characteristics of Hf-based gate dielectrics on strained-Si_1-xGe_x MOS devices

The physical and reliability characteristics of strained-Si _0.8Ge_0.2 MOS capacitor and strained-Si _0.7Ge_0.3 MOSFET with Hf-based gate dielectrics prepared by atomic layer chemical vapor deposition are investigated. The thickness and composition of the gate dielectrics are measured by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, respectively. The gate leakage current and interface traps of HfO₂/Si _1-xGe_x gate structure are slightly higher as compared to the HfO₂/Si MOS devices, which is basically caused by the Ge at the interface. The electrical properties of both HfO₂/Si and HfO ₂/Si_1-xGe_x devices can be improved with increasing PDA temperature up to 800°C, which is due to the thicker interfacial layer grown at the interface, even though crystallization also grows with increasing temperature. However, with higher PDA temperature (>800°C), serious crystallization of HfO₂ film causes more bulk traps induced electrical degradation. The electrical stress induced degradation of Si_1-xGe_x substrate is slightly higher as compared to the control Si, due to more traps generations at the HfO ₂/Si_1-xGe_x interface. For MOSFET, strained-Si_1-xGe_x can effectively improve the drain current for about 20% at saturation and 69% at linear region. The higher gate leakage (J_g ∼ 1.4 × 10^-9 A/cm² at 2 V) and lower breakdown voltage (BD ∼ 3.1 V) of Si_0.7Ge _0.3 pMOS devices are observed as compared to control Si devices (J_g ∼ 7.9 × 10^-12 A/cm² at 2 V and BD ∼ 7.4 V). After the electrical stress, the degradation of drain current and transconductance and the shift of threshold voltage for Si_1-xGe _x PMOSFET are larger than those for control Si devices, implying Ge induced trap generation at the Hf-silicate/Si_1-xGe_x interface.