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PLL鎖相迴路具有四相位輸出與低抖動

Translated title of the contribution: PLL phase-locked loop with four-phase output and low jitter
  • 蘇威全

Research output: Types of Thesis › Master's thesis

Translated title of the contributionPLL phase-locked loop with four-phase output and low jitter
Original languageChinese (Traditional)
Supervisors/Advisors
  • Kao, Shao-Ku, Supervisor
StatePublished - 2025
Externally publishedYes

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