Pulsewidth control loop with low control voltage ripple

A pulsewidth control loop (PWCL) with low control voltage ripple is proposed. The charge pump circuit with a charge-sharing circuit decreases the ripple of the control voltage, thus reducing the stability problem of the loop. The low control voltage ripple also reduces the jitter of the output clock. Simulations in a 0.18 μm CMOS process indicate that the input signal has a frequency range from 100 MHz to 1 GHz, and a duty cycle range from 40% to 60%. The proposed circuit can be used to reduce output clock jitters by 37.7% and 50.6%, respectively, for 1 GHz and 100 MHz.