Pulsewidth control loop with low control voltage ripple

Shao Ku Kao*, Yong De You

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A pulsewidth control loop (PWCL) with low control voltage ripple is proposed in this paper. The charge pump circuit with charge sharing circuit decreases the ripple of control voltage. By decreasing the control voltage ripple for reducing the stability problem of the loop. The jitter of the output clock is reduced due to the low control voltage ripple. It is demonstrated by simulation results in a 0.18pm CMOS process. The simulation shows that the frequency range of input signal is from 100MHz to 1GHz, the duty cycle range of the input signal is from 40% to 60%. The proposed circuit can reduce the output clock jitters by 37.7% and 50.6% for the 1GHz and 100MHz,respectiveIy.

Original languageEnglish
Title of host publicationInternational MultiConference of Engineers and Computer Scientists, IMECS 2012
PublisherNewswood Limited
Pages1075-1077
Number of pages3
ISBN (Print)9789881925190
StatePublished - 2012
Event2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012 - Kowloon, Hong Kong
Duration: 14 03 201216 03 2012

Publication series

NameLecture Notes in Engineering and Computer Science
Volume2196
ISSN (Print)2078-0958

Conference

Conference2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012
Country/TerritoryHong Kong
CityKowloon
Period14/03/1216/03/12

Keywords

  • Duty cycle corrector (DCC)
  • Fast locking
  • Lock detector
  • Low jitter
  • Pulsewidth control loops (PWCL)

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