Abstract
The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 |
| Publisher | IEEE Computer Society |
| Pages | 111-116 |
| Number of pages | 6 |
| ISBN (Electronic) | 0780372158 |
| DOIs | |
| State | Published - 2001 |
| Externally published | Yes |
| Event | 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 - Maui, United States Duration: 28 10 2001 → 30 10 2001 |
Publication series
| Name | Proceedings of the IEEE Conference on Nanotechnology |
|---|---|
| Volume | 2001-January |
| ISSN (Print) | 1944-9399 |
| ISSN (Electronic) | 1944-9380 |
Conference
| Conference | 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 |
|---|---|
| Country/Territory | United States |
| City | Maui |
| Period | 28/10/01 → 30/10/01 |
Bibliographical note
Publisher Copyright:© 2001 IEEE.