Quantum boolean circuit construction and layout under locality constraint

I. Ming Tsai, Sy Yen Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

19 Scopus citations

Abstract

The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit.

Original languageEnglish
Title of host publicationProceedings of the 2001 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
PublisherIEEE Computer Society
Pages111-116
Number of pages6
ISBN (Electronic)0780372158
DOIs
StatePublished - 2001
Externally publishedYes
Event1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 - Maui, United States
Duration: 28 10 200130 10 2001

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2001-January
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
Country/TerritoryUnited States
CityMaui
Period28/10/0130/10/01

Bibliographical note

Publisher Copyright:
© 2001 IEEE.

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