Reconfigurable cube-connected cycles architectures

In this paper two different approaches to designing reconfigurable cube-connected cycles parallel computation networks are proposed. Both architectures are capable of tolerating classes of multiple failures. The first approach is based on allocating spare processors and spare communication links in each cycle and utilizes local reconfiguration. The second approach is based on spare cycles (columns) and rows of processors and employs global reconfiguration techniques. Both of the approaches are shown to result in increases in reliability with reasonable increases in redundancy while maintaining many of the VLSI layout and implementation advantages of classical cube-connected cycles architectures.