Abstract
This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 μA conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.
| Original language | English |
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| Title of host publication | Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 318-321 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781479999286, 9781479999286 |
| DOIs | |
| State | Published - 25 08 2015 |
| Event | 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan Duration: 29 06 2015 → 02 07 2015 |
Publication series
| Name | Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA |
|---|---|
| Volume | 2015-August |
Conference
| Conference | 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 |
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| Country/Territory | Taiwan |
| City | Hsinchu |
| Period | 29/06/15 → 02/07/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.