Reliability assessment of self-timed VLSI circuits

Chen Hao Chang; Bing J. Sheu; Sudhir M. Gowda

Reliability assessment of self-timed VLSI circuits

Chen Hao Chang^*, Bing J. Sheu, Sudhir M. Gowda

^*Corresponding author for this work

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Self-timed LVSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Publisher	Publ by IEEE
Pages	30.3.1-30.3.4
ISBN (Print)	0780308263
State	Published - 1993
Externally published	Yes
Event	Proceedings of the IEEE 1993 Custom Integrated Circuits Conference - San Diego, CA, USA Duration: 09 05 1993 → 12 05 1993

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	Proceedings of the IEEE 1993 Custom Integrated Circuits Conference
City	San Diego, CA, USA
Period	09/05/93 → 12/05/93

Cite this

@inproceedings{f0b523fde54d40ed806860867ae65fd8,

title = "Reliability assessment of self-timed VLSI circuits",

abstract = "Self-timed LVSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented.",

author = "Chang, \{Chen Hao\} and Sheu, \{Bing J.\} and Gowda, \{Sudhir M.\}",

year = "1993",

language = "英语",

isbn = "0780308263",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Publ by IEEE",

pages = "30.3.1--30.3.4",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "Proceedings of the IEEE 1993 Custom Integrated Circuits Conference ; Conference date: 09-05-1993 Through 12-05-1993",

}

TY - GEN

T1 - Reliability assessment of self-timed VLSI circuits

AU - Chang, Chen Hao

AU - Sheu, Bing J.

AU - Gowda, Sudhir M.

PY - 1993

Y1 - 1993

N2 - Self-timed LVSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented.

AB - Self-timed LVSI circuits can avoid problems of clock distribution and achieve 500 MHz or higher-speed data processing. The RELY circuit reliability simulator is used to investigate the comparative reliability of two-phase, single-phase and self-timed circuits. Reliability simulation techniques and analysis results on submicron CMOS circuits are presented.

UR - https://www.scopus.com/pages/publications/0027271122

M3 - 会议稿件

AN - SCOPUS:0027271122

SN - 0780308263

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 30.3.1-30.3.4

BT - Proceedings of the Custom Integrated Circuits Conference

PB - Publ by IEEE

T2 - Proceedings of the IEEE 1993 Custom Integrated Circuits Conference

Y2 - 9 May 1993 through 12 May 1993

ER -

Reliability assessment of self-timed VLSI circuits

Abstract

Publication series

Conference

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Cite this