Abstract
This paper presents a method for circuit reliability evaluation. Based on the study of device reliability, a sub-circuit describing the device degradation after high-voltage stress is proposed. This model allows circuit reliability of VCOs to be evaluated and provides higher degree of freedom for circuit designers.
Original language | English |
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Pages | 377-380 |
Number of pages | 4 |
State | Published - 2003 |
Externally published | Yes |
Event | 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Philadelphia, PA, United States Duration: 08 06 2003 → 10 06 2003 |
Conference
Conference | 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium |
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Country/Territory | United States |
City | Philadelphia, PA |
Period | 08/06/03 → 10/06/03 |