Abstract
In this paper, we propose a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 12 × 12 bit ANT multiplier, circuit area in our fixed-width RPR can be lowered by 44.55% and power consumption in our ANT design can be saved by 23% as compared with the state-of-art ANT design.
Original language | English |
---|---|
Article number | 6740009 |
Pages (from-to) | 78-87 |
Number of pages | 10 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 23 |
Issue number | 1 |
DOIs | |
State | Published - 01 01 2015 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- Algorithmic noise tolerant (ANT)
- Fixed-width multiplier
- Reduced-precision replica (RPR)
- Voltage overscaling (VOS)