Abstract
It was found that the residual clamping force of bipolar electrostatic chucks created by the residual charge between a wafer and an electrode would not only cause a wafer sticking problem but also degrade dynamic random access memory (DRAM) data retention performance. The residual clamping force and data retention fail bit count (FBC) of DRAM showed strong correlations to the gate tungsten etch dechucking process condition. Wafer sticking only degraded DRAM cell retention performance, and did not influence any in-line measurement or electrical parameters. Electrical characterization analysis of the FBC proved that the retention loss was mainly due to junction leakage rather than gate-induced-drainleakage current. A new approach was proposed to suppress this leakage by introducing N 2 gas instead of O 2 to supply more plasma charges for neutralizing the wafer surface residual charges. The wafer shift dynamic alignment (DA) offset and retention FBC could be reduced by 50 and 40%, respectively. Poor data retention was suspected because of the compressive stress caused by wafer sticking DA shift resulting in a high electric field at the junction and an increase in junction leakage at the storage node.
Original language | English |
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Article number | 086502 |
Journal | Japanese Journal of Applied Physics |
Volume | 51 |
Issue number | 8 PART 1 |
DOIs | |
State | Published - 08 2012 |