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Reverse electrical behavior of N-channel and P-channel LTPS-TFTs by N2O plasma surface treatment

  • William Cheng Yu Ma*
  • , Chi Yuan Huang
  • , Tsung Chieh Chan
  • , Sheng Wei Yuan
  • *Corresponding author for this work
  • National Sun Yat-sen University

Research output: Contribution to journalJournal Article peer-review

1 Scopus citations

Abstract

In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction ΔVTH ∼ -0.57V, 1.55× higher transconductance Gm , and 1.82× higher driving current Idrv. However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase Δ VTH ∼-0.99 V, transconductance Gm reduction, and driving current Idrv degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit.

Original languageEnglish
Article number6847221
Pages (from-to)3825-3829
Number of pages5
JournalIEEE Transactions on Plasma Science
Volume42
Issue number12
DOIs
StatePublished - 01 12 2014
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 1973-2012 IEEE.

Keywords

  • 3-D integrated circuit (3-D IC)
  • HfO
  • interfacial layer
  • low-temperature poly-Si thin-film transistors (LTPS-TFTs)
  • plasma passivation.

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