Ringed bit-parallel systolic multipliers over a class of fields GF(2 m)

Yeun Renn Ting; Erl Huei Lu; Ya Cheng Lu

doi:10.1016/j.vlsi.2004.10.001

Ringed bit-parallel systolic multipliers over a class of fields GF(2 ^m)

Yeun Renn Ting
, Erl Huei Lu^*
, Ya Cheng Lu

^*Corresponding author for this work

Chang Gung University

Research output: Contribution to journal › Journal Article › peer-review

8 Scopus citations

Abstract

This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2^m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.

Original language	English
Pages (from-to)	571-578
Number of pages	8
Journal	Integration, the VLSI Journal
Volume	38
Issue number	4
DOIs	https://doi.org/10.1016/j.vlsi.2004.10.001
State	Published - 04 2005
Externally published	Yes

Keywords

AOP
Bit-parallel
ESP
Finite field
Systolic multiplier

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10.1016/j.vlsi.2004.10.001

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title = "Ringed bit-parallel systolic multipliers over a class of fields GF(2 m)",

abstract = "This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.",

keywords = "AOP, Bit-parallel, ESP, Finite field, Systolic multiplier",

author = "Ting, \{Yeun Renn\} and Lu, \{Erl Huei\} and Lu, \{Ya Cheng\}",

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AU - Lu, Erl Huei

AU - Lu, Ya Cheng

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N2 - This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.

AB - This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency and free of global connection. Furthermore, we proposed a general rule to plan the multipliers. This rule makes the planning easy.

KW - AOP

KW - Bit-parallel

KW - ESP

KW - Finite field

KW - Systolic multiplier

UR - https://www.scopus.com/pages/publications/14044263452

U2 - 10.1016/j.vlsi.2004.10.001

DO - 10.1016/j.vlsi.2004.10.001

M3 - 文章

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JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

IS - 4

ER -

Ringed bit-parallel systolic multipliers over a class of fields GF(2 ^m)

Abstract

Keywords

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