TY - JOUR
T1 - Scalable and systolic montgomery multipliers over GF(2m)
AU - Chen, Chin Chin
AU - Lee, Chiou Yng
AU - Lu, Eri Huei
PY - 2008
Y1 - 2008
N2 - This work presents a novel scalable and systolic Montgomery's algorithm in GF(2m). The proposed algorithm is based on the Toeplitz matrix-vector representation, which obtains the scalable and systolic Montgomery multiplier in a flexible manner, and can adapt to the required precision. Analytical results indicate that the proposed multiplier over the generic field of GF(2m) has a latency of d + n(2n +1), where n = [m/d], and d denotes the selected digital size. The latency is reduced to d + n(n + 1) clock cycles when the field is constructed from generalized equally-spaced polynomials. Since the selected digital size is d ≥ 5 bits, the proposed architectures have lower time-space complexity than traditional digit-serial multipliers. Moreover, the proposed architectures have regularity, modularity and local interconnect ability, making them very suitable for VLSI implementation.
AB - This work presents a novel scalable and systolic Montgomery's algorithm in GF(2m). The proposed algorithm is based on the Toeplitz matrix-vector representation, which obtains the scalable and systolic Montgomery multiplier in a flexible manner, and can adapt to the required precision. Analytical results indicate that the proposed multiplier over the generic field of GF(2m) has a latency of d + n(2n +1), where n = [m/d], and d denotes the selected digital size. The latency is reduced to d + n(n + 1) clock cycles when the field is constructed from generalized equally-spaced polynomials. Since the selected digital size is d ≥ 5 bits, the proposed architectures have lower time-space complexity than traditional digit-serial multipliers. Moreover, the proposed architectures have regularity, modularity and local interconnect ability, making them very suitable for VLSI implementation.
KW - Montgomery
KW - Scalable architecture
KW - Systolic multiplier
KW - Toeplitz matrix-vector
UR - http://www.scopus.com/inward/record.url?scp=77951261027&partnerID=8YFLogxK
U2 - 10.1093/ietfec/e91-a.7.1763
DO - 10.1093/ietfec/e91-a.7.1763
M3 - 文章
AN - SCOPUS:77951261027
SN - 0916-8508
VL - E91-A
SP - 1763
EP - 1771
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 7
ER -