Scaling VDD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved

Chao Ching Cheng; Ang Sheng Chou; Edward Chen; Ming Yang Li; Yu Wei Hsu; Chia Chin Cheng; Seong Rae Cho; Haomin Liu; Po Sen Mao; Wen Chia Wu; Shuer Ku; Wei Sheng Yun; Chih Piao Chuu; Wei Yen Woon; Lain Jong Li; Vincent Tung; Chih I. Wu; Iuliana Radu; Min Cao

doi:10.1109/VLSITechnologyandCir65830.2026.11577424

Scaling V_DD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved

Chao Ching Cheng^*
, Ang Sheng Chou
, Edward Chen
, Ming Yang Li
, Yu Wei Hsu
, Chia Chin Cheng
, Seong Rae Cho
, Haomin Liu
, Po Sen Mao
, Wen Chia Wu
, Shuer Ku
, Wei Sheng Yun
, Chih Piao Chuu
, Wei Yen Woon
, Lain Jong Li
, Vincent Tung
, Chih I. Wu
, Iuliana Radu
, Min Cao

^*Corresponding author for this work

Taiwan Semiconductor Manufacturing Company
National Taiwan University
The University of Tokyo
National University of Singapore

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This study investigates the effect of non-ideal factors in WSe2 2Dmaterial channel transistors, including interface traps (D_it), contact resistance (R_c), and band-tail states (S_BT), on the threshold voltage (V_T). For achieving the scaled V_DD=0.75 V operation, reduction of multiple non-idealities is required beyond current state: (i) reducing D_it below 1E12 cm^-2 eV^-1 preserves the position of V_TCC=-0.1 V (constant-current V_T); (ii) suppressing the SB T through gate dielectric engineering, with scaled EOT below 1 nm, is required for setting correct V_TCC and V_TGM (transconductance-defined V_T) positions; (iii) minimizing R_c to 100 Ω-μ m ensures the (VTGM-VTCC) gap below 0.28 V. The study combines these findings and offers insights to design the desired VT positions at scaled V_DD for 2D materials.

Original language	English
Title of host publication	2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331580964
DOIs	https://doi.org/10.1109/VLSITechnologyandCir65830.2026.11577424
State	Published - 2026
Externally published	Yes
Event	2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026 - Honolulu, United States Duration: 14 06 2026 → 18 06 2026

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562
ISSN (Electronic)	2158-9682

Conference

Conference	2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026
Country/Territory	United States
City	Honolulu
Period	14/06/26 → 18/06/26

Bibliographical note

Publisher Copyright:
© 2026 IEEE.

Access to Document

10.1109/VLSITechnologyandCir65830.2026.11577424

Cite this

Cheng, C. C., Chou, A. S., Chen, E., Li, M. Y., Hsu, Y. W., Cheng, C. C., Cho, S. R., Liu, H., Mao, P. S., Wu, W. C., Ku, S., Yun, W. S., Chuu, C. P., Woon, W. Y., Li, L. J., Tung, V., Wu, C. I., Radu, I., & Cao, M. (2026). Scaling V_DD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved. In 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir65830.2026.11577424

Cheng, Chao Ching ; Chou, Ang Sheng ; Chen, Edward et al. / Scaling V_DD for P-Type 2D-Material Channel Transistor : what Non-Idealities are Still to be Solved. 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., 2026. (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{8285248161e54ed5b343249054bd7e70,

title = "Scaling VDD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved",

abstract = "This study investigates the effect of non-ideal factors in WSe2 2Dmaterial channel transistors, including interface traps (Dit), contact resistance (Rc), and band-tail states (SBT), on the threshold voltage (VT). For achieving the scaled VDD=0.75 V operation, reduction of multiple non-idealities is required beyond current state: (i) reducing Dit below 1E12 cm-2 eV-1 preserves the position of VTCC=-0.1 V (constant-current VT); (ii) suppressing the SB T through gate dielectric engineering, with scaled EOT below 1 nm, is required for setting correct VTCC and VTGM (transconductance-defined VT) positions; (iii) minimizing Rc to 100 Ω-μ m ensures the (VTGM-VTCC) gap below 0.28 V. The study combines these findings and offers insights to design the desired VT positions at scaled VDD for 2D materials.",

author = "Cheng, \{Chao Ching\} and Chou, \{Ang Sheng\} and Edward Chen and Li, \{Ming Yang\} and Hsu, \{Yu Wei\} and Cheng, \{Chia Chin\} and Cho, \{Seong Rae\} and Haomin Liu and Mao, \{Po Sen\} and Wu, \{Wen Chia\} and Shuer Ku and Yun, \{Wei Sheng\} and Chuu, \{Chih Piao\} and Woon, \{Wei Yen\} and Li, \{Lain Jong\} and Vincent Tung and Wu, \{Chih I.\} and Iuliana Radu and Min Cao",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026 ; Conference date: 14-06-2026 Through 18-06-2026",

year = "2026",

doi = "10.1109/VLSITechnologyandCir65830.2026.11577424",

language = "英语",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026",

address = "美国",

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Cheng, CC, Chou, AS, Chen, E, Li, MY, Hsu, YW, Cheng, CC, Cho, SR, Liu, H, Mao, PS, Wu, WC, Ku, S, Yun, WS, Chuu, CP, Woon, WY, Li, LJ, Tung, V, Wu, CI, Radu, I & Cao, M 2026, Scaling V_DD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved. in 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026, Honolulu, United States, 14/06/26. https://doi.org/10.1109/VLSITechnologyandCir65830.2026.11577424

Scaling V_DD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved. / Cheng, Chao Ching; Chou, Ang Sheng; Chen, Edward et al.
2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc., 2026. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chen, Edward

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AU - Hsu, Yu Wei

AU - Cheng, Chia Chin

AU - Cho, Seong Rae

AU - Liu, Haomin

AU - Mao, Po Sen

AU - Wu, Wen Chia

AU - Ku, Shuer

AU - Yun, Wei Sheng

AU - Chuu, Chih Piao

AU - Woon, Wei Yen

AU - Li, Lain Jong

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AU - Wu, Chih I.

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N2 - This study investigates the effect of non-ideal factors in WSe2 2Dmaterial channel transistors, including interface traps (Dit), contact resistance (Rc), and band-tail states (SBT), on the threshold voltage (VT). For achieving the scaled VDD=0.75 V operation, reduction of multiple non-idealities is required beyond current state: (i) reducing Dit below 1E12 cm-2 eV-1 preserves the position of VTCC=-0.1 V (constant-current VT); (ii) suppressing the SB T through gate dielectric engineering, with scaled EOT below 1 nm, is required for setting correct VTCC and VTGM (transconductance-defined VT) positions; (iii) minimizing Rc to 100 Ω-μ m ensures the (VTGM-VTCC) gap below 0.28 V. The study combines these findings and offers insights to design the desired VT positions at scaled VDD for 2D materials.

AB - This study investigates the effect of non-ideal factors in WSe2 2Dmaterial channel transistors, including interface traps (Dit), contact resistance (Rc), and band-tail states (SBT), on the threshold voltage (VT). For achieving the scaled VDD=0.75 V operation, reduction of multiple non-idealities is required beyond current state: (i) reducing Dit below 1E12 cm-2 eV-1 preserves the position of VTCC=-0.1 V (constant-current VT); (ii) suppressing the SB T through gate dielectric engineering, with scaled EOT below 1 nm, is required for setting correct VTCC and VTGM (transconductance-defined VT) positions; (iii) minimizing Rc to 100 Ω-μ m ensures the (VTGM-VTCC) gap below 0.28 V. The study combines these findings and offers insights to design the desired VT positions at scaled VDD for 2D materials.

UR - https://www.scopus.com/pages/publications/105044698649

U2 - 10.1109/VLSITechnologyandCir65830.2026.11577424

DO - 10.1109/VLSITechnologyandCir65830.2026.11577424

M3 - 会议稿件

AN - SCOPUS:105044698649

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 14 June 2026 through 18 June 2026

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Cheng CC, Chou AS, Chen E, Li MY, Hsu YW, Cheng CC et al. Scaling V_DD for P-Type 2D-Material Channel Transistor: what Non-Idealities are Still to be Solved. In 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2026. Institute of Electrical and Electronics Engineers Inc. 2026. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir65830.2026.11577424