Simulated Annealing Hardware Architecture for Max-Cut Combinatorial Optimization

Combinational optimization (CO) is a pervasive concept in numerous fields, with the maximum cut problem representing a significant domain of CO applications, including image segmentation and circuit design. Simulated annealing is among the most prevalent methodologies for addressing combinatorial optimization challenges. This approach can expedite processing times while reducing the required area when implemented as a circuit. Additionally, simulated annealing with a fully connected architecture can directly resolve most problems. Therefore, a simulated annealing hardware architecture with a fully connected structure is chosen for implementation, and simplification is applied to the computationally complex parts. A fully connected simulated annealer with simplified computing units is proposed. The prototype chip, which supports a 9-spin fully connected graph, has been fabricated with the 180-nm CMOS technology and realized as a 0.963 x 0.960 mm² chip.