Simulation of EMI at design level for integrated circuits

Electromagnetic compatibility (EMC) analysis is mandatory due to the rapid increase in operating frequencies, RF interference and PCB layout density. Testing of IC layout is gaining importance as the electromagnetic interference (EMI) issues are increasingly problematic for an IC designer, and even becoming a critical factor for determining the performance of circuits at chip level. However, EMC/EMI testing is not reported at the IC on design level, and currently, for the EMC/EMI study on IC, chips are designed, fabricated and then tested for EMC/EMI and this is after the fact, and can be very costly and time consuming, especially for chips that operate at very high frequency. Hence, there is a great need for evaluating the EMC/EMI of IC at design level. In this work, a design methodology is demonstrated at IC design level by verifying its EMI. A Physically Unclonable Functions (PUF) IC chip is chosen for demonstration. The simulation results of its EMI spectrum using ADS software is verified experimentally using IC EMI scanner. Both IC-Scanner and ADS results agree well and they verify that the maximum noise-radiation peak is observed at a frequency of 17 MHz. The area and location of the maximum noise radiation are located in this work through the simulation.