Single-Phase Enhanced Phase-Locked Loops Based on Multiple Delayed Signal Cancellation Filters

Srinivas Gude, Chia Chi Chu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new single-phase (1f) filtering technique based on multiple delayed signal cancellation (MDSC) is proposed for extracting both in-phase and quadrature components of the selected harmonic order of the 1f grid voltage signal. This MDSC technique can be realized in both the direct-form and the recursive-form. In comparison with existing 1f cascaded delayed signal cancellation (CDSC) techniques, this MDSC technique utilizes less memory for the extraction of grid voltage fundamental frequency component. The proposed MDSC filter can be applied as a pre-filter to the enhanced phase-locked loop (EPLL) for the prompt and accurate estimations of the grid voltage information under adverse grid conditions. Both frequency adaptive and non-adaptive MDSC based EPLL schemes are studied in this paper. Experiments are conducted on the MDSC based EPLLs and compared with the CDSC-EPLL under various grid voltage disturbances.

Original languageEnglish
Title of host publication2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131535
DOIs
StatePublished - 11 2019
Externally publishedYes
Event4th IEEE International Future Energy Electronics Conference, IFEEC 2019 - Singapore, Singapore
Duration: 25 11 201928 11 2019

Publication series

Name2019 IEEE 4th International Future Energy Electronics Conference, IFEEC 2019

Conference

Conference4th IEEE International Future Energy Electronics Conference, IFEEC 2019
Country/TerritorySingapore
CitySingapore
Period25/11/1928/11/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

  • Delayed signal cancellation (DSC)
  • enhanced phase-locked loop (EPLL)
  • grid synchronization
  • harmonics
  • micro-grid

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