Abstract
In the wireless IoT applications, low power is a critical criteria, and low-voltage is a direct way to meet such demand. However, low-voltage criteria in advanced CMOS VLSI designs will lead to critical design challenges in dealing with soft-error interference, especial while the cascade transistor number is limited under low-voltage operations. Some possible low-voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Error-Correction with Duplication, dual interlocked storage cell (DICE) latch, and such as feedback redundant SEU-tolerant (FERST) latch designs.
| Original language | English |
|---|---|
| Title of host publication | ICUFN 2019 - 11th International Conference on Ubiquitous and Future Networks |
| Publisher | IEEE Computer Society |
| Pages | 179-181 |
| Number of pages | 3 |
| ISBN (Electronic) | 9781728113395 |
| DOIs | |
| State | Published - 07 2019 |
| Externally published | Yes |
| Event | 11th International Conference on Ubiquitous and Future Networks, ICUFN 2019 - Zagreb, Croatia Duration: 02 07 2019 → 05 07 2019 |
Publication series
| Name | International Conference on Ubiquitous and Future Networks, ICUFN |
|---|---|
| Volume | 2019-July |
| ISSN (Print) | 2165-8528 |
| ISSN (Electronic) | 2165-8536 |
Conference
| Conference | 11th International Conference on Ubiquitous and Future Networks, ICUFN 2019 |
|---|---|
| Country/Territory | Croatia |
| City | Zagreb |
| Period | 02/07/19 → 05/07/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.