Speed-enhanced CMOS level shifting circuits for VLSI applications

Hwang Cherng Chow*

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review


Speed-enhanced CMOS level shifting circuits are proposed for mixed voltage applications. In circuits embodying this invention, the main advantage as compared to the prior art is one more pair path to charge and discharge the output nodes simultaneously, which leads to a less PMOS to NMOS ratio problem. Therefore, the output low-to-high transition becomes faster due to charging enhancement in the initial phase. The high-to-low transition also becomes faster because of discharging enhancement in the transition period.

Original languageEnglish
Pages (from-to)72-76
Number of pages5
JournalWSEAS Transactions on Electronics
Issue number2
StatePublished - 04 2005


  • CMOS
  • Level shifting
  • Low power
  • Mixed voltage
  • Ratio problem
  • VLSI


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