Statistical modeling of via redundancy effects on interconnect reliability

  • Nagarajan Raghavan*
  • , Cher Ming Tan
  • *Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study.

Original languageEnglish
Title of host publication2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
Duration: 07 07 200811 07 2008

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Country/TerritorySingapore
CitySingapore
Period07/07/0811/07/08

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