Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

Chia Ming Yang, Jer Chyi Wang, Wei Ping Lee, Chien Chi Lee, Chih Hung Lin, Chung Yuan Lee, Jo Hui Lin, Hsin Huei Chen, Chih Yuan Hsiao, Ruey Dar Chang, Chao Sung Lai

Research output: Contribution to journalJournal Article peer-review

11 Scopus citations

Abstract

A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

Original languageEnglish
Article number6553604
Pages (from-to)1124-1126
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number9
DOIs
StatePublished - 2013

Keywords

  • Dynamic random access memory (DRAM)
  • fluorine (F) implantation
  • gate-induced drain leakage (GIDL)
  • retention

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