Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

Chia Ming Yang; Jer Chyi Wang; Wei Ping Lee; Chien Chi Lee; Chih Hung Lin; Chung Yuan Lee; Jo Hui Lin; Hsin Huei Chen; Chih Yuan Hsiao; Ruey Dar Chang; Chao Sung Lai

doi:10.1109/LED.2013.2271274

Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

Chia Ming Yang, Jer Chyi Wang, Wei Ping Lee, Chien Chi Lee, Chih Hung Lin, Chung Yuan Lee, Jo Hui Lin, Hsin Huei Chen, Chih Yuan Hsiao, Ruey Dar Chang, Chao Sung Lai

Research output: Contribution to journal › Journal Article › peer-review

15 Scopus citations

Abstract

A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

Original language	English
Article number	6553604
Pages (from-to)	1124-1126
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	34
Issue number	9
DOIs	https://doi.org/10.1109/LED.2013.2271274
State	Published - 2013

Keywords

Dynamic random access memory (DRAM)
fluorine (F) implantation
gate-induced drain leakage (GIDL)
retention

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Yang, C. M., Wang, J. C., Lee, W. P., Lee, C. C., Lin, C. H., Lee, C. Y., Lin, J. H., Chen, H. H., Hsiao, C. Y., Chang, R. D., & Lai, C. S. (2013). Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology. IEEE Electron Device Letters, 34(9), 1124-1126. Article 6553604. https://doi.org/10.1109/LED.2013.2271274

@article{7bbc98b56bf840c89ff2099e7df79a35,

title = "Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology",

abstract = "A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.",

keywords = "Dynamic random access memory (DRAM), fluorine (F) implantation, gate-induced drain leakage (GIDL), retention",

author = "Yang, {Chia Ming} and Wang, {Jer Chyi} and Lee, {Wei Ping} and Lee, {Chien Chi} and Lin, {Chih Hung} and Lee, {Chung Yuan} and Lin, {Jo Hui} and Chen, {Hsin Huei} and Hsiao, {Chih Yuan} and Chang, {Ruey Dar} and Lai, {Chao Sung}",

year = "2013",

doi = "10.1109/LED.2013.2271274",

language = "英语",

volume = "34",

pages = "1124--1126",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

AU - Yang, Chia Ming

AU - Wang, Jer Chyi

AU - Lee, Wei Ping

AU - Lee, Chien Chi

AU - Lin, Chih Hung

AU - Lee, Chung Yuan

AU - Lin, Jo Hui

AU - Chen, Hsin Huei

AU - Hsiao, Chih Yuan

AU - Chang, Ruey Dar

AU - Lai, Chao Sung

PY - 2013

Y1 - 2013

N2 - A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

AB - A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

KW - Dynamic random access memory (DRAM)

KW - fluorine (F) implantation

KW - gate-induced drain leakage (GIDL)

KW - retention

UR - http://www.scopus.com/inward/record.url?scp=84883154295&partnerID=8YFLogxK

U2 - 10.1109/LED.2013.2271274

DO - 10.1109/LED.2013.2271274

M3 - 文章

AN - SCOPUS:84883154295

SN - 0741-3106

VL - 34

SP - 1124

EP - 1126

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 9

M1 - 6553604

ER -

Superior improvements in GIDL and retention by fluorine implantation in saddle-fin array devices for sub-40-nm DRAM technology

Abstract

Keywords

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