Systolic array for modulo 2^N-1 adder

This investigation presents a new algorithm for modulo (2^N - 1) addition. The idea is that the result of two N-bit numbers going through N + 1 rows of N half-adders is same as the result of the conventional algorithm for addition modulo (2^N - 1). According to this new idea, a new systolic array for modulo (2^N - 1) adder is designed. Its computing speed is 1/(the delay time of an half-adder and a register). It is faster than the conventional design. Moreover, the clock numbers of latency waiting for output is N + 1. It is less than the conventional design.