Testing of analog neural array-processor chips

Wen Jay Hsu; Bing J. Sheu; Sudhir M. Gowda

Testing of analog neural array-processor chips

Wen Jay Hsu^*, Bing J. Sheu, Sudhir M. Gowda

^*Corresponding author for this work

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Systematic testing is of significant importance to assure the quality and reliability of VLSI neural chips. In a general-purpose neural chip, the neuron array and synapse matrix can be tested in a sequence. The test results of a programmable analog neural chip, which was fabricated by a 2-μm CMOS process, are presented. This chip contains 25 neurons and 1,600 synapses.

Original language	English
Title of host publication	IEEE International Conference on Computer Design - VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	118-121
Number of pages	4
ISBN (Print)	0818622709
State	Published - 1991
Externally published	Yes
Event	Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91 - Cambridge, MA, USA Duration: 14 10 1991 → 16 10 1991

Publication series

Name	IEEE International Conference on Computer Design - VLSI in Computers and Processors

Conference

Conference	Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91
City	Cambridge, MA, USA
Period	14/10/91 → 16/10/91

Cite this

@inproceedings{5775228f24664d17bc6fbd08e73e5b2d,

title = "Testing of analog neural array-processor chips",

abstract = "Systematic testing is of significant importance to assure the quality and reliability of VLSI neural chips. In a general-purpose neural chip, the neuron array and synapse matrix can be tested in a sequence. The test results of a programmable analog neural chip, which was fabricated by a 2-μm CMOS process, are presented. This chip contains 25 neurons and 1,600 synapses.",

author = "Hsu, {Wen Jay} and Sheu, {Bing J.} and Gowda, {Sudhir M.}",

year = "1991",

language = "英语",

isbn = "0818622709",

series = "IEEE International Conference on Computer Design - VLSI in Computers and Processors",

publisher = "Publ by IEEE",

pages = "118--121",

booktitle = "IEEE International Conference on Computer Design - VLSI in Computers and Processors",

note = "Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91 ; Conference date: 14-10-1991 Through 16-10-1991",

}

Hsu, WJ, Sheu, BJ & Gowda, SM 1991, Testing of analog neural array-processor chips. in IEEE International Conference on Computer Design - VLSI in Computers and Processors. IEEE International Conference on Computer Design - VLSI in Computers and Processors, Publ by IEEE, pp. 118-121, Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91, Cambridge, MA, USA, 14/10/91.

Testing of analog neural array-processor chips. / Hsu, Wen Jay; Sheu, Bing J.; Gowda, Sudhir M.
IEEE International Conference on Computer Design - VLSI in Computers and Processors. Publ by IEEE, 1991. p. 118-121 (IEEE International Conference on Computer Design - VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Testing of analog neural array-processor chips

AU - Hsu, Wen Jay

AU - Sheu, Bing J.

AU - Gowda, Sudhir M.

PY - 1991

Y1 - 1991

N2 - Systematic testing is of significant importance to assure the quality and reliability of VLSI neural chips. In a general-purpose neural chip, the neuron array and synapse matrix can be tested in a sequence. The test results of a programmable analog neural chip, which was fabricated by a 2-μm CMOS process, are presented. This chip contains 25 neurons and 1,600 synapses.

AB - Systematic testing is of significant importance to assure the quality and reliability of VLSI neural chips. In a general-purpose neural chip, the neuron array and synapse matrix can be tested in a sequence. The test results of a programmable analog neural chip, which was fabricated by a 2-μm CMOS process, are presented. This chip contains 25 neurons and 1,600 synapses.

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M3 - 会议稿件

AN - SCOPUS:0026297386

SN - 0818622709

T3 - IEEE International Conference on Computer Design - VLSI in Computers and Processors

SP - 118

EP - 121

BT - IEEE International Conference on Computer Design - VLSI in Computers and Processors

PB - Publ by IEEE

T2 - Proceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91

Y2 - 14 October 1991 through 16 October 1991

ER -

Testing of analog neural array-processor chips

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