Testing transition delay faults in modified Booth multipliers

This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and 27 patterns, respectively. These patterns can be generated by using a linear feedback shift register or a finite state machine, requiring a modest increase of 5% area for our 32 × 32 multiplier, for example. In addition, a method is proposed to generate 51% to 99% fewer patterns for the realistic sequential cell fault model (RS-CFM), when compared with a recent work. RS-CFM faults, which are claimed to be comprehensive in modeling sequential fault effects inside the cells, require all possible single-input-change patterns prepared for each cell. The proposed method generates 104 + 10 × N_Y test pairs for RS-CFM in the N _X × N_Y modified Booth multiplier to achieve a similar fault coverage as the cited work.