The acceleration of pipeline workloads under the FPGA area and bandwidth constraints

Wei Ning Huang; Sheng Wei Cheng; Che Wei Chang; Yu Chen Wu; Tei Wei Kuo; Yung Chin Hsu; Wen Yih Isaac Tseng; Shih Hao Hung

doi:10.1109/RTCSA.2014.6910539

The acceleration of pipeline workloads under the FPGA area and bandwidth constraints

Wei Ning Huang^*, Sheng Wei Cheng, Che Wei Chang, Yu Chen Wu, Tei Wei Kuo, Yung Chin Hsu, Wen Yih Isaac Tseng, Shih Hao Hung

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this paper explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where the FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental results, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.

Original language	English
Title of host publication	RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479939534
DOIs	https://doi.org/10.1109/RTCSA.2014.6910539
State	Published - 25 09 2014
Event	20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2014 - Chongqing, China Duration: 20 08 2014 → 22 08 2014

Publication series

Name	RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

Conference

Conference	20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2014
Country/Territory	China
City	Chongqing
Period	20/08/14 → 22/08/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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10.1109/RTCSA.2014.6910539

Cite this

Huang, W. N., Cheng, S. W., Chang, C. W., Wu, Y. C., Kuo, T. W., Hsu, Y. C., Tseng, W. Y. I., & Hung, S. H. (2014). The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. In RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications Article 6910539 (RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RTCSA.2014.6910539

Huang, Wei Ning ; Cheng, Sheng Wei ; Chang, Che Wei et al. / The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. Institute of Electrical and Electronics Engineers Inc., 2014. (RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications).

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title = "The acceleration of pipeline workloads under the FPGA area and bandwidth constraints",

abstract = "This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this paper explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where the FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental results, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.",

author = "Huang, {Wei Ning} and Cheng, {Sheng Wei} and Chang, {Che Wei} and Wu, {Yu Chen} and Kuo, {Tei Wei} and Hsu, {Yung Chin} and Tseng, {Wen Yih Isaac} and Hung, {Shih Hao}",

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year = "2014",

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day = "25",

doi = "10.1109/RTCSA.2014.6910539",

language = "英语",

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Huang, WN, Cheng, SW, Chang, CW, Wu, YC, Kuo, TW, Hsu, YC, Tseng, WYI & Hung, SH 2014, The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. in RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications., 6910539, RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Institute of Electrical and Electronics Engineers Inc., 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2014, Chongqing, China, 20/08/14. https://doi.org/10.1109/RTCSA.2014.6910539

The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. / Huang, Wei Ning; Cheng, Sheng Wei; Chang, Che Wei et al.
RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. Institute of Electrical and Electronics Engineers Inc., 2014. 6910539 (RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Huang, Wei Ning

AU - Cheng, Sheng Wei

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AU - Tseng, Wen Yih Isaac

AU - Hung, Shih Hao

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N2 - This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this paper explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where the FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental results, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.

AB - This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this paper explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where the FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental results, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.

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Huang WN, Cheng SW, Chang CW, Wu YC, Kuo TW, Hsu YC et al. The acceleration of pipeline workloads under the FPGA area and bandwidth constraints. In RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. Institute of Electrical and Electronics Engineers Inc. 2014. 6910539. (RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications). doi: 10.1109/RTCSA.2014.6910539

The acceleration of pipeline workloads under the FPGA area and bandwidth constraints

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