The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation

Shing Yih Shih; Jian Jang Cheng; Chi Hsiang Kuo; Chang Rang Wu; Jeng Ping Lin; Pei Ing Lee

The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation

Shing Yih Shih, Jian Jang Cheng, Chi Hsiang Kuo, Chang Rang Wu, Jeng Ping Lin, Pei Ing Lee

Nanya Technology Corporation

Research output: Contribution to conference › Conference Paper › peer-review

Abstract

As chip size shrinkage, similar to the pattern density effect, topography effect of STI structure would also strongly influence CMP performance due to STI filling process getting complication. In this paper, the STI topography effect on SiN erosion of direct ceria slurry CMP was studied on four different STI topography structures created by three different fill approaches on 110nm ground rule with AR∼4 and ∼8, in respectively. Besides, the performances of two kinds of ceria slurry with different selectivity of oxide to SiN were also compared.

Original language	English
Pages	197-200
Number of pages	4
State	Published - 2005
Externally published	Yes
Event	22nd International VLSI Multilevel Interconnection Conference, VMIC 2005 - Fremont, CA, United States Duration: 04 10 2005 → 06 10 2005

Conference

Conference	22nd International VLSI Multilevel Interconnection Conference, VMIC 2005
Country/Territory	United States
City	Fremont, CA
Period	04/10/05 → 06/10/05

Cite this

@conference{5c3944bffa164aa68bbbaff001d99910,

title = "The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation",

abstract = "As chip size shrinkage, similar to the pattern density effect, topography effect of STI structure would also strongly influence CMP performance due to STI filling process getting complication. In this paper, the STI topography effect on SiN erosion of direct ceria slurry CMP was studied on four different STI topography structures created by three different fill approaches on 110nm ground rule with AR∼4 and ∼8, in respectively. Besides, the performances of two kinds of ceria slurry with different selectivity of oxide to SiN were also compared.",

author = "Shih, {Shing Yih} and Cheng, {Jian Jang} and Kuo, {Chi Hsiang} and Wu, {Chang Rang} and Lin, {Jeng Ping} and Lee, {Pei Ing}",

year = "2005",

language = "英语",

pages = "197--200",

note = "22nd International VLSI Multilevel Interconnection Conference, VMIC 2005 ; Conference date: 04-10-2005 Through 06-10-2005",

}

The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation. / Shih, Shing Yih; Cheng, Jian Jang; Kuo, Chi Hsiang et al.
2005. 197-200 Paper presented at 22nd International VLSI Multilevel Interconnection Conference, VMIC 2005, Fremont, CA, United States.

Research output: Contribution to conference › Conference Paper › peer-review

TY - CONF

T1 - The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation

AU - Shih, Shing Yih

AU - Cheng, Jian Jang

AU - Kuo, Chi Hsiang

AU - Wu, Chang Rang

AU - Lin, Jeng Ping

AU - Lee, Pei Ing

PY - 2005

Y1 - 2005

N2 - As chip size shrinkage, similar to the pattern density effect, topography effect of STI structure would also strongly influence CMP performance due to STI filling process getting complication. In this paper, the STI topography effect on SiN erosion of direct ceria slurry CMP was studied on four different STI topography structures created by three different fill approaches on 110nm ground rule with AR∼4 and ∼8, in respectively. Besides, the performances of two kinds of ceria slurry with different selectivity of oxide to SiN were also compared.

AB - As chip size shrinkage, similar to the pattern density effect, topography effect of STI structure would also strongly influence CMP performance due to STI filling process getting complication. In this paper, the STI topography effect on SiN erosion of direct ceria slurry CMP was studied on four different STI topography structures created by three different fill approaches on 110nm ground rule with AR∼4 and ∼8, in respectively. Besides, the performances of two kinds of ceria slurry with different selectivity of oxide to SiN were also compared.

UR - http://www.scopus.com/inward/record.url?scp=84888320299&partnerID=8YFLogxK

M3 - 论文

AN - SCOPUS:84888320299

SP - 197

EP - 200

T2 - 22nd International VLSI Multilevel Interconnection Conference, VMIC 2005

Y2 - 4 October 2005 through 6 October 2005

ER -

The effects of wafer topography after STI fill on ceria slurry CMP for beyond 110nm generation

Abstract

Conference

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