The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET

The impact of interface/border defect on performance and reliability was investigated for gate-first and gate-last high-k/metal-gate CMOSFET. For high-k/metal-gate CMOSFET, V_FB roll-off is critical as effective oxide thickness (EOT) scales below 15 angstrom (Å) especially for metal gate-first device with an extra capping layer to adjust V_TH. By proposing a model of metal-gate process induced interface trap releasing oxygen, the vertical and lateral interface trap distribution and the dependence of interfacial layer (IL) on V_FB roll-off phenomena can be well interpreted. In this work, we found that V_FB roll-off can be improved by reducing oxygen vacancy (V_O) at the HfO₂/IL interface with suppression of oxygen diffusion from high-k to IL. By the way, a metal gate-last process with lower interface trap was proposed to minimize V _O formation by suppress oxygen releasing, thus optimize a 28 nm 15 Å EOT HfO₂/metal-gate CMOSFET with low V_FB-EOT roll-off, it can be a reference for sub 22 nm CMOSFET with thin EOT (<15 Å) design.