The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

S. S. Chung*, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen, M. S. Liang

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

1 Scopus citations

Abstract

In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the ID degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the ID degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced VT shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔVT in thin-oxide with reduced width.

Original languageEnglish
Pages279-282
Number of pages4
StatePublished - 2004
EventProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan
Duration: 05 07 200408 07 2004

Conference

ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country/TerritoryTaiwan
Period05/07/0408/07/04

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