Abstract
As interconnects dominate circuit performance in modern chip designs, placement becomes an essential stage in optimizing timing. Recent timing-driven placement (TDP) techniques focus mainly on optimizing late slack rather than early slack. This paper presents a TDP algorithm to improve the early slack while preserving an optimized late slack. The preservation is achieved by accurately predicting optimal Steiner tree topologies after each move in our TDP algorithm. An optimality-preserving pruning scheme for each move is proposed to speed up the optimization process, without sacrificing the solution quality. Experimental results show that our algorithm can substantially improve the early slacks and the overall quality scores of the top-2 winning placers of the 2015 ICCAD Incremental Timing-Driven Placement Contest, while preserving their late slacks.
Original language | English |
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Title of host publication | Proceedings of the 53rd Annual Design Automation Conference, DAC 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781450342360 |
DOIs | |
State | Published - 05 06 2016 |
Externally published | Yes |
Event | 53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States Duration: 05 06 2016 → 09 06 2016 |
Publication series
Name | Proceedings - Design Automation Conference |
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Volume | 05-09-June-2016 |
ISSN (Print) | 0738-100X |
Conference
Conference | 53rd Annual ACM IEEE Design Automation Conference, DAC 2016 |
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Country/Territory | United States |
City | Austin |
Period | 05/06/16 → 09/06/16 |
Bibliographical note
Publisher Copyright:© 2016 ACM.
Keywords
- Physical design
- Placement
- Steiner tree
- Timing