Two-stage reconfigurable computing system architecture

There are many successful applications of reconfigurable computing architecture in the past decade. They can be implemented into reconfigurable computing system according to their function algorithms usually. But, due to the influence of Gordon Moore's Law on FPGA (field programmable gate arrays) structure, the gate array sizes have been expanded widely under the technology of ULSI (ultra large scale integration). So, Using FPGAs to implement the design of function level is waste of reconfigurable units. Therefore, how to build a powerful reconfigurable computing architecture is an important research topic. In this article, a new reconfigurable computing architecture named TSRCS (two-stage reconfigurable computing system) is proposed. The concept of TSRCS is to split the reconfiguration into two stages, one is SSR (system-stage reconfiguration) and another is FSR (function-stage reconfiguration). The SSR dynamically rebuilds routing networks that connect between RFBs (reconfigurable function blocks) but the FSR busily reconfigures RFBs following some computing algorithm that we want to do. The TSRCS can dynamic change not only the system architecture but also any function. The advantages of using TSRCS to implement a system are architecture flexible, function varied, system opening and performance changeable but the disadvantage is construction longer. In this paper, a new design method is proposed which can combine the forte of software and hardware to build a new system architecture and the research results have important contribution to computer science.