V-band CMOS differential-type injection locked frequency dividers

While the operation frequency of the wireless and the wire-used modern communication systems has being extended to millimeter-wave band, the timing circuits also become important for the low-cost and performance concerns, such as synthesizer or frequency divider. As the millimeter-wave wireless local area network (WLAN) transmitting a digital modulated data upon a carrier frequency through a antenna, is proposed to either obtain a broadcasting service in local area or provide the flexible data access. For the requirement of synchronization, hence the high speed and high frequency dividers/prescalars up to 60 GHz may be employed in phase-locked loop (PLL). Moreover, the power consumption and the low noise features in the divider circuits are also the major concerns. Conventional common-mode logic (CML) dividers are difficult to push the maximum operation frequency to over the microwave range due to its limitation by the cut-off frequency f_T, regardless it reaches a wide dividing range. Extreme high power consumption is also the disadvantage for CML approach. Thus to fulfill the low power dissipation dividers, the LC-type injection-locked frequency dividers, (ILFD) have been proposed and being used in PLL or clock-data recovery (CDR) circuits [1]. The CMOS sub-micron techniques have been progressed to a proper high frequency divider design. In this work, there are two 60 GHz ILFDs have been realized by using the CMOS 0.18μm 1P6M technology, in which contain the self-oscillation frequencies of 30 GHz and 15 GHz respectively for a divided-by 2 or 4 operation. Both ILEDs demonstrate the improved locking ranges using a self-oscillation frequency tuning and a 0/180° single-to-differential power divider with low dc power consumptions.