Abstract
In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 288 Mb/s and consume 32.7 mW while operating at a 72 Mhz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
| Original language | English |
|---|---|
| Pages (from-to) | IV57-IV60 |
| Journal | Materials Research Society Symposium - Proceedings |
| Volume | 626 |
| State | Published - 2001 |
| Externally published | Yes |
| Event | Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 04 2000 → 27 04 2000 |