TY - GEN
T1 - VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation
AU - Lai, Yeong Kang
AU - Shu, Yu Chuan
PY - 2001
Y1 - 2001
N2 - In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 /spl mu/ CMOS technology. The chip can achieve an encryption rate of 288 Mb/a and consume 32.7 mW while operating at a 72 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
AB - In this paper, a novel VLSI architecture of the BLOWFISH block cipher is presented. Based on the loop-folding technique combined with secure modes (ECB, CBC2, CFB2 and OFB2) of operation, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 /spl mu/ CMOS technology. The chip can achieve an encryption rate of 288 Mb/a and consume 32.7 mW while operating at a 72 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.
UR - http://www.scopus.com/inward/record.url?scp=33646502717&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922168
DO - 10.1109/ISCAS.2001.922168
M3 - 会议稿件
AN - SCOPUS:33646502717
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 57
EP - 60
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -