VLSI architecture design and implementation for TWOFISH block cipher

Yeong Kang Lai, Jian Yi Lai, Tai Ming Parng

Research output: Contribution to journalJournal Article peer-review

3 Scopus citations

Abstract

In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

Original languageEnglish
Pages (from-to)356-359
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 2002
Externally publishedYes

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