VLSI architecture design and implementation for TWOFISH block cipher

Yeong Kang Lai; Jian Yi Lai; Tai Ming Parng

doi:10.1109/ISCAS.2002.1010998

VLSI architecture design and implementation for TWOFISH block cipher

Yeong Kang Lai
, Jian Yi Lai
, Tai Ming Parng

National Chung Hsing University

Research output: Contribution to journal › Journal Article › peer-review

4 Scopus citations

Abstract

In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

Original language	English
Pages (from-to)	356-359
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2002.1010998
State	Published - 2002
Externally published	Yes

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@article{6fe02c711b30477e909acde324010595,

title = "VLSI architecture design and implementation for TWOFISH block cipher",

abstract = "In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.",

author = "Lai, \{Yeong Kang\} and Lai, \{Jian Yi\} and Parng, \{Tai Ming\}",

year = "2002",

doi = "10.1109/ISCAS.2002.1010998",

language = "英语",

volume = "2",

pages = "356--359",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - VLSI architecture design and implementation for TWOFISH block cipher

AU - Lai, Yeong Kang

AU - Lai, Jian Yi

AU - Parng, Tai Ming

PY - 2002

Y1 - 2002

N2 - In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

AB - In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μ CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

UR - https://www.scopus.com/pages/publications/0036290527

U2 - 10.1109/ISCAS.2002.1010998

DO - 10.1109/ISCAS.2002.1010998

M3 - 文章

AN - SCOPUS:0036290527

SN - 0271-4310

VL - 2

SP - 356

EP - 359

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

VLSI architecture design and implementation for TWOFISH block cipher

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