VLSI architectures for median filtering with linear complexity

Erl Huei Lu*, Jau Yien Lee, Yawpo Yang

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

2 Scopus citations

Abstract

Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

Original languageEnglish
Pages358-362
Number of pages5
StatePublished - 1996
EventProceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) - Perth, Aust
Duration: 26 11 199629 11 1996

Conference

ConferenceProceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2)
CityPerth, Aust
Period26/11/9629/11/96

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