Abstract
Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.
Original language | English |
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Pages | 358-362 |
Number of pages | 5 |
State | Published - 1996 |
Event | Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) - Perth, Aust Duration: 26 11 1996 → 29 11 1996 |
Conference
Conference | Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) |
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City | Perth, Aust |
Period | 26/11/96 → 29/11/96 |