VLSI architectures for median filtering with linear complexity

Erl Huei Lu; Jau Yien Lee; Yawpo Yang

VLSI architectures for median filtering with linear complexity

Erl Huei Lu^*
, Jau Yien Lee
, Yawpo Yang

^*Corresponding author for this work

Department of Electrical Engineering

Chang Gung University

Research output: Contribution to conference › Conference Paper › peer-review

2 Scopus citations

Abstract

Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

Original language	English
Pages	358-362
Number of pages	5
State	Published - 1996
Event	Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) - Perth, Aust Duration: 26 11 1996 → 29 11 1996

Conference

Conference	Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2)
City	Perth, Aust
Period	26/11/96 → 29/11/96

Cite this

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title = "VLSI architectures for median filtering with linear complexity",

abstract = "Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.",

author = "Lu, \{Erl Huei\} and Lee, \{Jau Yien\} and Yawpo Yang",

year = "1996",

language = "英语",

pages = "358--362",

note = "Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2) ; Conference date: 26-11-1996 Through 29-11-1996",

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AU - Lu, Erl Huei

AU - Lee, Jau Yien

AU - Yang, Yawpo

PY - 1996

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AB - Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.

UR - https://www.scopus.com/pages/publications/0030312188

M3 - 论文

AN - SCOPUS:0030312188

SP - 358

EP - 362

T2 - Proceedings of the 1996 IEEE Region 10 TENCON - Digital Signal Processing Applications Conference. Part 2 (of 2)

Y2 - 26 November 1996 through 29 November 1996

ER -

VLSI architectures for median filtering with linear complexity

Abstract

Conference

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