VLSI image processor using analog programmable synapses and neurons

Bang W. Lee; Ji Chien Lee; Bing J. Sheu

VLSI image processor using analog programmable synapses and neurons

Bang W. Lee^*, Ji Chien Lee, Bing J. Sheu

^*Corresponding author for this work

University of Southern California

Research output: Contribution to conference › Conference Paper › peer-review

8 Scopus citations

Abstract

A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6 × 6.8 mm² in a MOSIS 2-μm CMOS process and achieves 300× speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm² silicon area.

Original language	English
Pages	575-580
Number of pages	6
State	Published - 1990
Externally published	Yes
Event	1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) - San Diego, CA, USA Duration: 17 06 1990 → 21 06 1990

Conference

Conference	1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)
City	San Diego, CA, USA
Period	17/06/90 → 21/06/90

Cite this

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title = "VLSI image processor using analog programmable synapses and neurons",

abstract = "A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6 × 6.8 mm2 in a MOSIS 2-μm CMOS process and achieves 300× speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm2 silicon area.",

author = "Lee, {Bang W.} and Lee, {Ji Chien} and Sheu, {Bing J.}",

year = "1990",

language = "英语",

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note = "1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3) ; Conference date: 17-06-1990 Through 21-06-1990",

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AU - Lee, Bang W.

AU - Lee, Ji Chien

AU - Sheu, Bing J.

PY - 1990

Y1 - 1990

N2 - A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6 × 6.8 mm2 in a MOSIS 2-μm CMOS process and achieves 300× speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm2 silicon area.

AB - A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6 × 6.8 mm2 in a MOSIS 2-μm CMOS process and achieves 300× speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm2 silicon area.

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M3 - 论文

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T2 - 1990 International Joint Conference on Neural Networks - IJCNN 90 Part 3 (of 3)

Y2 - 17 June 1990 through 21 June 1990

ER -

VLSI image processor using analog programmable synapses and neurons

Abstract

Conference

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